University of Houston

Software pipelining is a technique used to schedule instructions from a loop body so that multiple iterations of the loop are executing in parallel. This can be accomplished by taking advantage of instruction level parallelism (ILP). ILP is a combination of compilation techniques and architectural features that exploit the fine-grain parallelism present at the machine instruction level. Superscalar and very long instruction word (VLIW) processors are designed to exploit ILP. Multicore processors are designed to exploit course grain Thread Level Parallelism (TLP).

The first part of this dissertation proposal provides background on clustered architectures that are capable of exploiting ILP and TLP. We discuss cluster assignment and software pipelining for an inner loop on an ILP architecture. We then expand this solution to perform cluster assignment and software pipelining on a loop nest. We then modify our loop nest scheduler to consider a hybrid ILP/TLP architecture, where analysis will be made to determine how to tradeoff ILP and TLP to best execute the loop nest. In doing this, we improve existing algorithms for performing cluster assignment, software pipelining for ILP, and ILP/TLP combined scheduling for loop nests.