High performance processors attempt to increase the instruction
execution rate by allowing more than one instruction to be issued
and executed in parallel whenever possible. This significantly
increases the complexity of processors, largely because of the need
to keep multiple functional units synchronized. At the same time, the
additional complexity also makes it more difficulty to simulate
program execution on these processors accurately.
In this thesis, we study an already existent simulation environment,
the Simple Scalar Simulator, and analyze its advantages and
limitations for the architecture and compiler research. We examine
the simulation of a computer architecture, which includes the
instruction set, the register file, function units and the memory. To
construct a simulation/evaluation environment to fit the special need
of the research group, we modify the Simple Scalar assembler so
that it can support the assembly annotation. At the same time, we
extend simulator instruction decoding and implement a simulation
scheme to simulate a new branch prediction method. To verify the
modified simulator, we simulate this new branch prediction scheme
and test it on SPEC95 benchmark programs. The simulation result
indicates that the modified simulator can meet some special
requirement of the architecture and compiler.